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The CMOS technology plays a major role on the motion of microprocessors on very outsized scale integrated roach chips. The rapid growth in CMOS technology with theshrinking transistor size towards 16nm has allowed forplacement of several billions of transistors on a hitmicroprocessor chip. This also leads to reduce the delay of logicgates in the order of pico seconds. One such method to improvethe performance of microprocessor is to optimize the timingperformance of slashing circuits. In this paper a profuse addercircuit is designed and simulated victimization rate sensing keepertechnique with L=0.12m technology and VDD=1.2 V forimproving the timing and noise tolerance also the noise tolerancecharacteristics of the full adder circuit designed utilise ratesensing keeper is compared with twin transistor based full addercircuit.Keywords Bias,Domino logic, noise tolerance, rate sensing,timing optimization.I. INTRODUCTIONHE rapid onward motion in semiconductor technology withthe sh rinking transistor size towards 16nm has allowed forplacement of several billion transistors on a singlemicroprocessor chip1. CMOS technology plays a major roleon the performance of VLSI microprocessors 2.The timingperformance of the microprocessor stop be improved by usingdynamic circuits in microprocessors 3. However the usage ofdynamic circuits in microprocessors is limited due to manychallenges including transistor sizing, charge sharing, leakage underway, noise immunity and environmental and semiconductorprocess variations etc 4.Timing optimization of dynamiccircuits can be achieved through several methods such astransistor sizing, using multiple threshold voltagesetc.5,6,7.The aggressive scaling of transistors andinterc... ... andthe experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique givessuperior performance compared to the another(prenominal) alternatives suchas Conditional Keeper (CKP) and current mirror-based ke eper(LCR).Fig.22. Output noise Vs Vbias characteristics of full adder using Rate SensingKeeper techniqueIV. CONCLUSIONIn this paper the performance of a full adder circuitdesigned using rate sensing keeper transistor technique isanalyzed in detail and its performance is compared with otherfull adder circuits. The full adder circuit is simulated usingL=0.12m technology along with supply voltage VDD=1.2V.The experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique givessuperior performance compared to full adder circuits designedusing conventional domino techniques.